1. Field of the Invention
The present invention relates to the fabrication of integrated circuits. More particularly, the invention relates to a method for depositing dielectric layers on a substrate and structures that include the dielectric layer.
2. Description of the Related Art
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices that will fit on a chip doubles every two years. Today's fabrication plants are routinely producing devices having 0.13 μm and even 0.1 μm feature sizes, and tomorrow's plants soon will be producing devices having even smaller geometries.
In order to further reduce the size of devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and to use insulators having low dielectric constants (k) to reduce the capacitive coupling between adjacent metal lines. One such low k material is spin-on glass, such as un-doped silicon glass (USG) or fluorine-doped silicon glass (FSG), which can be deposited as a gap fill layer in a semiconductor manufacturing process. Other examples of low k materials include carbon doped silicon dioxide and polytetrafluoroethylene. However, the continued reduction in device geometries has generated a demand for films having even lower k values.
Recent developments in low dielectric constants have focused on incorporating silicon, carbon, and oxygen atoms into the deposited film. One challenge in this area has been to develop a Si, C, and O containing film that has a low k value, but also exhibits desirable thermal and mechanical properties. Most often, films made of a Si, C, and O network that have the lowest dielectric constant exhibit poor mechanical strength and are easily damaged by etch chemistry and subsequent plasma exposure, causing failure of the integrated circuit.
Therefore, there is a need for a process for making low dielectric constant materials that would improve the speed and efficiency of devices on integrated circuits as well as the durability and mechanical integrity of the integrated circuit.